The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 31, 2016

Filed:

Oct. 30, 2013
Applicant:

Ibiden Co., Ltd., Ogaki-shi, JP;

Inventors:

Kazuhiro Yoshikawa, Ogaki, JP;

Liyi Chen, Ogaki, JP;

Toshiki Furutani, Ogaki, JP;

Assignee:

IBIDEN CO., LTD., Ogaki-shi, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/18 (2006.01); H05K 3/46 (2006.01); H01L 23/498 (2006.01); H01L 23/538 (2006.01); H05K 1/16 (2006.01);
U.S. Cl.
CPC ...
H05K 3/4644 (2013.01); H01L 23/49822 (2013.01); H01L 23/49827 (2013.01); H01L 23/5383 (2013.01); H01L 23/5384 (2013.01); H01L 23/5389 (2013.01); H05K 3/4602 (2013.01); H05K 3/4694 (2013.01); H01L 2924/0002 (2013.01); H05K 1/165 (2013.01); H05K 1/185 (2013.01); H05K 2201/10015 (2013.01); H05K 2201/10636 (2013.01); H05K 2203/1469 (2013.01); Y02P 70/611 (2015.11); Y10T 29/4913 (2015.01);
Abstract

A printed wiring board includes a core substrate having opening, an electronic component device accommodated in the opening of the substrate and including inductor and passive components, a wiring structure connecting the inductor and passive components in the electronic device, a filler resin body filling space formed between the substrate and electronic device in the opening of the substrate, a first buildup layer including a first interlayer insulation layer on first surface of the substrate, a first conductive layer on the first insulation layer, and a first via conductor in the first insulation layer, and a second buildup layer including a second interlayer insulation layer on second surface of the substrate on the opposite side of the first surface of the substrate, a second conductive layer on the second insulation layer, and a second via conductor in the second insulation layer.


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