The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 31, 2016

Filed:

May. 07, 2013
Applicant:

Csmc Technologies Fab1 Co., Ltd., Wuxi, Jiangsu, CN;

Inventors:

Shu Zhang, Wuxi, CN;

Yanqiang He, Wuxi, CN;

TseHuang Lo, Wuxi, CN;

HsiaoChia Wu, Wuxi, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 23/00 (2006.01); H01L 23/482 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7816 (2013.01); H01L 23/4824 (2013.01); H01L 24/02 (2013.01); H01L 24/05 (2013.01); H01L 24/06 (2013.01); H01L 24/07 (2013.01); H01L 24/08 (2013.01); H01L 24/09 (2013.01); H01L 29/7835 (2013.01); H01L 2924/1306 (2013.01); H01L 2924/13091 (2013.01);
Abstract

Various embodiments of a power MOS device structure are disclosed. In one aspect, a power MOS device structure includes a plurality of LDMOS and a plurality of bonding pads. The basic units of LDMOS are coupled in parallel and electrically coupled to the bonding pads to couple to a gate terminal, a source terminal, a drain terminal and a substrate of each of the basic units of LDMOS. The basic units of LDMOS are disposed below the bonding pads. The bonding pads include a single layer of metal with a thickness of 3.5 um to 4.5 um and a width of 1.5 um to 2.5 um. The region below the bonding pads of the power MOS device of the present disclosure is utilized to increase the number of basic units of LDMOS, thereby effectively reducing the on-resistance.


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