The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9356124 B1

PDF
Full Text
Expired
Date of Patent:
May. 31, 2016

Filed:

Sep. 30, 2013
Applicant:

Peking University, Beijing, CN;

Inventors:

Ru Huang, Beijing, CN;

Jiewen Fan, Beijing, CN;

Jia Li, Beijing, CN;

Xiaoyan Xu, Beijing, CN;

Ming Li, Beijing, CN;

Assignee:

Peking University, Beijing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 29/66 (2006.01); H01L 21/02 (2006.01); H01L 21/311 (2006.01); H01L 21/762 (2006.01); H01L 21/3105 (2006.01); H01L 21/265 (2006.01); H01L 21/324 (2006.01); H01L 21/3065 (2006.01); H01L 29/08 (2006.01); H01L 21/28 (2006.01); H01L 21/285 (2006.01); H01L 29/51 (2006.01); H01L 21/321 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66795 (2013.01); H01L 21/0217 (2013.01); H01L 21/0228 (2013.01); H01L 21/02164 (2013.01); H01L 21/02181 (2013.01); H01L 21/26513 (2013.01); H01L 21/2855 (2013.01); H01L 21/28088 (2013.01); H01L 21/28556 (2013.01); H01L 21/3065 (2013.01); H01L 21/31055 (2013.01); H01L 21/31116 (2013.01); H01L 21/324 (2013.01); H01L 21/3212 (2013.01); H01L 21/76224 (2013.01); H01L 29/0847 (2013.01); H01L 29/513 (2013.01); H01L 29/517 (2013.01); H01L 29/66545 (2013.01); H01L 29/66575 (2013.01);
Abstract

A method for fabricating a multi-gate structure device with a source and a drain having a quasi-SOI structure, comprising forming an active region in a shape of a fin bar, forming an oxide isolation layer for shallow trench isolation (STI), forming a polysilicon dummy gate, forming source and drain extension regions, forming the source and the drain with the quasi-SOI structure, and forming a high-K metal gate. Solution(s) consistent with the present innovations may be achieved by using a process method compatible with the conventional bulk silicon CMOS processes and can be easily integrated into the process flow. Moreover, innovations here may provide a small leakage current even in a case of having a short channel length, thereby reducing the power consumption of the device.


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