The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 31, 2016

Filed:

Feb. 05, 2014
Applicant:

Renesas Electronics Corporation, Kanagawa, JP;

Inventors:

Masao Inoue, Kanagawa, JP;

Yoshiki Maruyama, Kanagawa, JP;

Akio Nishida, Kanagawa, JP;

Yorinobu Kunimune, Kanagawa, JP;

Kota Funayama, Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/28 (2006.01); H01L 29/40 (2006.01); H01L 29/49 (2006.01); H01L 29/423 (2006.01); H01L 21/02 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/4925 (2013.01); H01L 21/0245 (2013.01); H01L 21/02488 (2013.01); H01L 21/02502 (2013.01); H01L 21/02532 (2013.01); H01L 21/02667 (2013.01); H01L 21/28035 (2013.01); H01L 21/28176 (2013.01); H01L 21/28273 (2013.01); H01L 29/42324 (2013.01); H01L 29/4916 (2013.01); H01L 29/66825 (2013.01);
Abstract

To control a grain growth on laminated polysilicon films, a method of manufacturing a semiconductor device is provided. The method includes: forming a first polysilicon film () on a substrate (); forming an interlayer oxide layer () on a surface of the first polysilicon film (); forming a second polysilicon film () in contact with the interlayer oxide layer () above the first polysilicon film (); and performing annealing at a temperature higher than a film formation temperature of the first and second polysilicon films in a gas atmosphere containing nitrogen, after formation of the second polysilicon film ().


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