The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 31, 2016

Filed:

May. 14, 2014
Applicant:

Maxim Integrated Products, Inc., San Jose, CA (US);

Inventors:

Nicole D. Kerness, Menlo Park, CA (US);

Arkadii V. Samoilov, Saratoga, CA (US);

Jerome C. Bhat, Palo Alto, CA (US);

Anand Chamakura, San Jose, CA (US);

Kumar Nagarajan, Cupertino, CA (US);

Christopher F. Edwards, Sunnyvale, CA (US);

Assignee:

Maxim Integrated Products, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
F21V 14/00 (2006.01); G01J 1/04 (2006.01); G01J 1/02 (2006.01); G01J 1/08 (2006.01); G01J 1/42 (2006.01);
U.S. Cl.
CPC ...
G01J 1/0411 (2013.01); G01J 1/0271 (2013.01); G01J 1/08 (2013.01); G01J 1/4204 (2013.01);
Abstract

A wafer level optical device, system, and method are described that include a substrate, an electronic device disposed on the substrate, an illumination source disposed on the electronic device, an enclosure disposed on the substrate, where the enclosure includes at least one optical surface and covers the electronic device and the illumination source, and at least one solder ball disposed on a side of the substrate distal from the electronic device. In implementations, a process for using the wafer level optical device and lens-integrated package system that employ the techniques of the present disclosure includes receiving a substrate, placing an electronic device on the substrate, placing an illumination source on the electronic device, and placing an enclosure on the substrate, where the enclosure covers the electronic device and the illumination source, and the enclosure and a wall structure form a first compartment and a second compartment.


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