The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 24, 2016

Filed:

Jul. 17, 2013
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Jean-Pierre Colinge, Hsin-Chu, TW;

Kuo-Cheng Ching, Zhubei, TW;

Gwan Sin Chang, Hsin-Chu, TW;

Zhiqiang Wu, Chubei, TW;

Chih-Hao Wang, Baoshan Township, TW;

Carlos H. Diaz, Mountain View, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 21/762 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/78 (2013.01); H01L 21/02104 (2013.01); H01L 21/76224 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 29/7848 (2013.01);
Abstract

A method includes performing a first epitaxy to grow a silicon germanium layer over a semiconductor substrate, performing a second epitaxy to grow a silicon layer over the silicon germanium layer, and performing a first oxidation to oxidize the silicon germanium layer, wherein first silicon germanium oxide regions are generated. A strain releasing operation is performed to release a strain caused by the first silicon germanium oxide regions. A gate dielectric is formed on a top surface and a sidewall of the silicon layer. A gate electrode is formed over the gate dielectric.


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