The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 24, 2016
Filed:
Nov. 18, 2014
United Microelectronics Corp., Hsin-Chu, TW;
Chih-Wei Yang, Kaohsiung, TW;
Yu-Feng Liu, Tainan, TW;
Jian-Cun Ke, Tainan, TW;
Chia-Fu Hsu, Tainan, TW;
En-Chiuan Liou, Tainan, TW;
Ssu-I Fu, Kaohsiung, TW;
Chi-Mao Hsu, Tainan, TW;
Nien-Ting Ho, Tainan, TW;
Yu-Ru Yang, Hsinchu County, TW;
Yu-Ping Wang, Taoyuan County, TW;
Chien-Ming Lai, Tainan, TW;
Yi-Wen Chen, Tainan, TW;
Yu-Ting Tseng, Tainan, TW;
Ya-Huei Tsai, Tainan, TW;
Chien-Chung Huang, Tainan, TW;
Tsung-Yin Hsieh, Tainan, TW;
Hung-Yi Wu, Keelung, TW;
UNITED MICROELECTRONICS CORP., Science-Based Industrial Park, Hsin-Chu, TW;
Abstract
A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having an interlayer dielectric (ILD) layer thereon; forming a first recess, a second recess, and a third recess in the ILD layer; forming a material layer on the ILD layer and in the first recess, the second recess, and the third recess; performing a first treatment on the material layer in the first recess; and performing a second treatment on the material layer in the first recess and second recess.