The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 24, 2016

Filed:

Jun. 04, 2015
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Tsung-Liang Chen, Cohoes, NY (US);

Hung-Wei Liu, Saratoga Springs, NY (US);

Rohit Pal, Clifton Park, NY (US);

Hsin-Neng Tai, Clifton Park, NY (US);

Huey-Ming Wang, Ballston Lake, NY (US);

Tae Hoon Lee, Clifton Park, NY (US);

Songkram Srivathanakul, Waterford, NY (US);

Danni Chen, Clifton Park, NY (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/76 (2006.01); H01L 29/423 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01);
U.S. Cl.
CPC ...
H01L 29/42364 (2013.01); H01L 21/823828 (2013.01); H01L 21/823857 (2013.01); H01L 21/823864 (2013.01); H01L 27/092 (2013.01);
Abstract

Methods of facilitating gate height uniformity by controlling recessing of dielectric material and semiconductor devices formed from the methods are provided. The methods include, for instance, forming a transistor of the semiconductor device with an n-type transistor and a p-type transistor, the n-type transistor and the p-type transistor including plurality of sacrificial gate structures and protective masks at upper surfaces of the plurality of sacrificial gate structures; providing a dielectric material over and between the plurality of sacrificial gate structures; partially densifying the dielectric material to form a partially densified dielectric material; further densifying the partially densified dielectric material to create a modified dielectric material; and creating substantially planar surface on the modified dielectric material, to control dielectric material recess and gate height.


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