The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 24, 2016

Filed:

Jan. 29, 2014
Applicant:

Transphorm Japan, Inc., Yokohama, Kanagawa, JP;

Inventors:

Yuji Ito, Hachioji, JP;

Yuko Matsui, Kodaira, JP;

Yoshiyuki Kotani, Aizuwakamatsu, JP;

Assignee:

Transphorm Japan, Inc., Yokohama, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/20 (2006.01); H01L 29/778 (2006.01); H01L 29/40 (2006.01);
U.S. Cl.
CPC ...
H01L 29/2003 (2013.01); H01L 29/402 (2013.01); H01L 29/66462 (2013.01); H01L 29/7787 (2013.01);
Abstract

A semiconductor apparatus includes a substrate; a first semiconductor layer formed on the substrate and formed of a nitride semiconductor; a second semiconductor layer formed on the first semiconductor layer and formed of a nitride semiconductor; first and second gate electrodes, a source electrode, and a drain electrode formed on the second semiconductor layer; an interlayer insulation film formed on the second semiconductor layer; and a field plate formed on the interlayer insulation film. Further, the first gate electrode and the second gate electrode are formed between a region where the source electrode is formed and a region where the field plate is formed, an element isolation region is formed in the first and the second semiconductor layers which are between the first and the second gate electrodes, and the second gate electrode is electrically connected to the source electrode.


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