The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 24, 2016
Filed:
Jul. 09, 2015
Assembly structure for connecting multiple dies into a system-in-package chip and the method thereof
Tsung Chuan Whang, Cupertino, CA (US);
Yi-chieh Wang, Taichung, TW;
Tsung Chuan Whang, Cupertino, CA (US);
Yi-Chieh Wang, Taichung, TW;
Global Unichip Corp., Hsinchu, TW;
Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;
Abstract
A method for assembling multiple integrated circuit dies into a system-in-package chip is disclosed, the method comprising: providing a plurality of integrated circuit dies; disposing at least one redistribution layer on at least one of the plurality of integrated circuit dies for making wire connections among the plurality of integrated circuit dies without using a substrate underneath the plurality of integrated circuit dies; establishing wire connections among the plurality of integrated circuit dies and verifying the plurality of wire connections; and packaging the plurality of integrated circuit dies and the verified wire connections into a system-in-package chip.