The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 17, 2016

Filed:

Mar. 13, 2013
Applicant:

Freescale Semiconductor, Inc., Austin, TX (US);

Inventors:

Xu Cheng, Chandler, AZ (US);

Daniel J. Blomberg, Chandler, AZ (US);

Zhihong Zhang, Chandler, AZ (US);

Jiang-Kai Zuo, Chandler, AZ (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/72 (2006.01); H01L 29/06 (2006.01); H01L 27/108 (2006.01); H01L 21/761 (2006.01); H01L 21/8238 (2006.01); H01L 21/762 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0611 (2013.01); H01L 21/761 (2013.01); H01L 21/76224 (2013.01); H01L 21/76237 (2013.01); H01L 21/823878 (2013.01); H01L 27/10876 (2013.01);
Abstract

An integrated semiconductor device includes a substrate of a first conductivity type, a buried layer located over the substrate, an isolated region located over a first portion of the buried layer, and an isolation trench located around the isolated region. A punch-through structure is located around at least a portion of the isolation trench. The punch-through structure includes a second portion of the buried layer, a first region located over the second portion of the buried layer, the first region having a second conductivity type, and a second region located over the first region, the second region having the first conductivity type.


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