The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 17, 2016

Filed:

Nov. 05, 2013
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Ho-Jin Lee, Seoul, KR;

Tae-Je Cho, Hwaseong-si, KR;

Dong-Hyeon Jang, Yongin-si, KR;

Ho-Geon Song, Suwon-si, KR;

Se-Young Jeong, Suwon-si, KR;

Un-Byoung Kang, Hwaseong-si, KR;

Min-Seung Yoon, Seoul, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/76 (2006.01); H01L 21/326 (2006.01); H01L 21/768 (2006.01); H01L 23/48 (2006.01); H01L 25/065 (2006.01); H01L 23/525 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76898 (2013.01); H01L 23/481 (2013.01); H01L 25/0657 (2013.01); H01L 23/525 (2013.01); H01L 2224/16 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06544 (2013.01);
Abstract

In one embodiment, a semiconductor device includes a semiconductor substrate having a first surface, and a second surface opposite to the first surface. The second surface defines a redistribution trench. The substrate has a via hole extending therethrough. The semiconductor device also includes a through via disposed in the via hole. The through via may include a via hole insulating layer, a barrier layer, sequentially formed on an inner wall of the via hole. The through via may further include a conductive connector adjacent the barrier layer. The semiconductor device additionally includes an insulation layer pattern formed on the second surface of the substrate. The insulation layer pattern defines an opening that exposes a region of a top surface of the through via. The semiconductor devices includes a redistribution layer disposed in the trench and electrically connected to the through via. The insulation layer pattern overlaps a region of the conductive connector.


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