The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 17, 2016
Filed:
Apr. 01, 2014
Xilinx, Inc., San Jose, CA (US);
Ganesh Hariharan, Santa Clara, CA (US);
Raghunandan Chaware, Sunnyvale, CA (US);
Glenn O'Rourke, Gilroy, CA (US);
Inderjit Singh, Saratoga, CA (US);
Eric J. Thorne, Santa Cruz, CA (US);
David E. Schweigler, Copperopolis, CA (US);
XILNIX, INC., San Jose, CA (US);
Abstract
A testable circuit arrangement includes an integrated circuit (IC) package. The IC package includes a package substrate, an interposer mounted directly on the package substrate with level 1 interconnects, and at least one IC die mounted directly on the interposer with level 0 interconnects. The package substrate of the IC package is mounted directly on a connector board with a soldered ball grid array of level 2 interconnects. The level 0, level 1, and level 2 interconnects include respective power, configuration, and test interconnects. Power, configuration, and test terminals of the connector board are coupled to the power, configuration, and test interconnects of the level 2 interconnects.