The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 10, 2016

Filed:

Nov. 27, 2013
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Chen-Hao Li, Kaohsiung, TW;

Ying-Han Chiou, Tainan, TW;

Chi-Yen Lin, Tainan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 21/768 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/481 (2013.01); H01L 21/76838 (2013.01); H01L 24/03 (2013.01); H01L 24/05 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 24/81 (2013.01); H01L 2224/0345 (2013.01); H01L 2224/03452 (2013.01); H01L 2224/03462 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/0557 (2013.01); H01L 2224/05624 (2013.01); H01L 2224/05647 (2013.01); H01L 2224/05684 (2013.01); H01L 2224/13022 (2013.01); H01L 2224/13025 (2013.01); H01L 2224/16235 (2013.01); H01L 2224/16238 (2013.01); H01L 2224/81193 (2013.01); H01L 2924/157 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/37001 (2013.01);
Abstract

An integrated circuit and a method of fabricating the integrated circuit are provided. In various embodiments, the integrated circuit includes a first substrate, a second substrate, and a bump pad. The first substrate has at least one active device and a plurality of first metallic pads electrically connected to the active device. The first substrate has front-end-of-line processing layers without back-end-of-line processing layers over the front-end-of-line processing layers. The second substrate has a semiconductor substrate and an interconnect structure disposed on the semiconductor substrate, and the interconnect structure has at least one second metallic pad. The second substrate does not include any active devices. The bump pad is sandwiched by the first substrate and the second substrate. The active device and the first metallic pad of the first substrate are electrically connected to the second metallic pad of the second substrate through the bump pad.


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