The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 03, 2016

Filed:

Jan. 26, 2015
Applicant:

Maxim Integrated Products, Inc., San Jose, CA (US);

Inventors:

Quanbo Zou, Plano, TX (US);

Uppili Sridhar, Plano, TX (US);

Amit S. Kelkar, Flower Mound, TX (US);

Xuejun Ying, San Jose, CA (US);

Assignee:

Maxim Integrated Products, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/02 (2006.01); H01L 23/48 (2006.01); H01L 23/52 (2006.01); H01L 29/40 (2006.01); H01L 23/00 (2006.01); B81C 3/00 (2006.01); C25D 7/12 (2006.01); C25D 17/00 (2006.01); H01L 25/00 (2006.01);
U.S. Cl.
CPC ...
H01L 24/83 (2013.01); B81C 3/001 (2013.01); C25D 7/123 (2013.01); C25D 17/001 (2013.01); C25D 17/005 (2013.01); C25D 17/007 (2013.01); H01L 23/481 (2013.01); H01L 25/50 (2013.01); B81C 2201/0197 (2013.01); B81C 2203/035 (2013.01); H01L 24/13 (2013.01); H01L 24/94 (2013.01); H01L 2224/13144 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06541 (2013.01); H01L 2924/01068 (2013.01); H01L 2924/10253 (2013.01); H01L 2924/12042 (2013.01); H01L 2924/1461 (2013.01); H01L 2924/30101 (2013.01);
Abstract

A method including: providing a first wafer stack; applying a first bonding layer on the first wafer stack; providing a second wafer stack, where the second wafer stack includes vias; and applying a second bonding layer to the second wafer stack. The vias extend through the second wafer stack and to the second bonding layer. The second bonding layer is bonded to the first bonding layer. A seed layer is applied on a side of the second wafer stack opposite the second bonding layer such that a material of the seed layer (i) contacts the vias, and (ii) extends over and past ends of the second wafer stack and onto the first bonding layer.


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