The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 03, 2016
Filed:
Dec. 28, 2012
Intel Corporation, Santa Clara, CA (US);
Paolo Narvaez, Wayland, MA (US);
Ganapati N. Srinivasa, Portland, OR (US);
Eugene Gorbatov, Hillsboro, OR (US);
Dheeraj R. Subbareddy, Hillsboro, OR (US);
Mishali Naik, Santa Clara, CA (US);
Alon Naveh, Ramat Hasharon, IL;
Abirami Prabhakaran, Hillsboro, OR (US);
Eliezer Weissmann, Haifa, IL;
David A. Koufaty, Portland, OR (US);
Paul Brett, Hillsboro, OR (US);
Scott D. Hahn, Beaverton, OR (US);
Andrew J. Herdrich, Hillsboro, OR (US);
Ravishankar Iyer, Portland, OR (US);
Nagabhushan Chitlur, Portland, OR (US);
Inder M. Sodhi, Folsom, CA (US);
Gaurav Khanna, Hillsboro, OR (US);
Russell J. Fenger, Beaverton, OR (US);
INTEL CORPORATION, Santa Clara, CA (US);
Abstract
A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a first set of one or more physical processor cores having first processing characteristics; a second set of one or more physical processor cores having second processing characteristics different from the first processing characteristics; virtual-to-physical (V-P) mapping logic to expose a plurality of virtual processors to software, the plurality of virtual processors to appear to the software as a plurality of homogeneous processor cores, the software to allocate threads to the virtual processors as if the virtual processors were homogeneous processor cores; wherein the V-P mapping logic is to map each virtual processor to a physical processor within the first set of physical processor cores or the second set of physical processor cores such that a thread allocated to a first virtual processor by software is executed by a physical processor mapped to the first virtual processor from the first set or the second set of physical processors.