The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 26, 2016

Filed:

Apr. 17, 2015
Applicant:

Shinko Electric Industries Co., Ltd, Nagano-ken, JP;

Inventors:

Yasuyoshi Horikawa, Nagano, JP;

Tatsuaki Denda, Nagano, JP;

Assignee:

Shinko Electric Industries Co., Ltd., Nagano-shi, Nagano-ken, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 33/64 (2010.01); H01L 33/62 (2010.01); H05K 1/02 (2006.01); H05K 3/10 (2006.01); H01L 33/60 (2010.01); H05K 1/18 (2006.01);
U.S. Cl.
CPC ...
H01L 33/642 (2013.01); H01L 33/60 (2013.01); H01L 33/62 (2013.01); H01L 33/647 (2013.01); H05K 1/0204 (2013.01); H05K 1/0206 (2013.01); H01L 33/641 (2013.01); H01L 2224/16225 (2013.01); H01L 2924/15192 (2013.01); H05K 1/0207 (2013.01); H05K 1/18 (2013.01); H05K 2201/10106 (2013.01);
Abstract

A wiring substrate includes a heat sink, an insulation layer, first and second wiring layers, first and second through wirings, and first and second pads. The insulation layer is arranged on the heat sink with an adhesive layer located in between. The insulation layer includes first and second through holes. The first and second wiring layers are arranged on a surface of the insulation layer in contact with the adhesive layer. The first and second wiring layers are embedded in the adhesive layer. The first through wiring formed in the first through hole is connected to the first wiring layer and thermally coupled to the semiconductor device. The second through wiring formed in the first through hole is connected to the second wiring layer and electrically connected to the semiconductor device. The pads cover exposed surfaces of the through wirings.


Find Patent Forward Citations

Loading…