The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 26, 2016

Filed:

Aug. 19, 2014
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Ran Ruby Yan, Dresden, DE;

Ralf Richter, Dresden, DE;

Jan Hoentschel, Dresden, DE;

Hans-Jurgen Thees, Dresden, DE;

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 21/84 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 21/762 (2006.01); H01L 21/306 (2006.01); H01L 21/02 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7853 (2013.01); H01L 21/02532 (2013.01); H01L 21/02587 (2013.01); H01L 21/02639 (2013.01); H01L 21/30608 (2013.01); H01L 21/30625 (2013.01); H01L 21/76224 (2013.01); H01L 21/76283 (2013.01); H01L 29/0653 (2013.01); H01L 29/66795 (2013.01); H01L 29/7855 (2013.01);
Abstract

FinFET devices with epitaxially grown fins and methods for fabricating them are provided. Embodiments include forming at least two shallow trench isolation (STI) regions, filled with dielectric material, adjacent to but separate from each other in a silicon substrate; epitaxially growing a silicon-based layer between each adjacent pair of STI regions to form a fin with a non-rectangular cross-section extending from each STI region to each adjacent STI region; forming a gate oxide over and perpendicular to each fin; and forming a gate electrode over the gate oxide to form a FinFET.


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