The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 26, 2016

Filed:

Dec. 18, 2014
Applicant:

Powertech Technology Inc., Hsinchu County, TW;

Inventor:

Wen-Jeng Fan, Hsinchu County, TW;

Assignee:

Powertech Technology Inc., Hsinchu County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/02 (2006.01); H01L 23/522 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5226 (2013.01); H01L 24/49 (2013.01); H01L 2924/183 (2013.01);
Abstract

A package structure includes a chip, a substrate, wires and a molding compound. The chip includes an active surface, a back surface and bonding pads disposed on the active surface. The substrate includes first and second solder masks, first and second patterned circuit layers and a core layer having a first surface and a second surface. The first patterned circuit layer is disposed on the first solder mask. The core layer disposed on the first solder mask with the first surface partially exposes the first patterned circuit layer. The substrate disposed on the active surface with the first solder mask exposes the bonding pads. The second patterned circuit layer disposed on the second surface. The second solder mask partially covers the second patterned circuit layer. The wires are connected between the first patterned circuit layer and the bonding pads. The molding compound covers the chip, the wire and the substrate.


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