logo

For the Inventor, By the Inventor

The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9324583 B1

PDFFull Text
Date of Patent:
Apr. 26, 2016

Filed:

Jan. 20, 2012

Packaging method

Applicants:

Lei Shi, Nantong, CN;

Yujuan Tao, Nantong, CN;

Guohua Gao, Nantong, CN;

Jaingen Shi, Nantong, CN;

Haiqing Zhu, Nantong, CN;

Inventors:

Lei Shi, Nantong, CN;

Yujuan Tao, Nantong, CN;

Guohua Gao, Nantong, CN;

Jaingen Shi, Nantong, CN;

Haiqing Zhu, Nantong, CN;

Assignee:

NANTONG FUJITSU MICROELECTRONICS CO., LTD., Nantong, CN;

Attorney:

RatnerPrestia

Primary Examiner:

Mary Wilczewski

Assistant Examiner:

Erik T Peterson

Int. Cl.
CPC ...
H01L 21/52 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 23/538 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 21/52 (2013.01); H01L 21/561 (2013.01); H01L 21/568 (2013.01); H01L 23/3128 (2013.01); H01L 23/49816 (2013.01); H01L 23/5389 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 24/96 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/24195 (2013.01); H01L 2924/12042 (2013.01); H01L 2924/181 (2013.01); H01L 2924/1815 (2013.01); H01L 2924/19105 (2013.01);
Abstract

The present invention relates to a packaging method including the steps: a cementing layer is formed on a carrier board; the functional sides of chips and passive devices are attached to the cementing layer; a sealing material layer is formed on the side of the carrier board to which the chips and the passive devices are attached, and packaging and curing are performed; and the carrier board and the cementing layer are removed. Compared to the prior art, the system-level fan-out wafer packaging method claimed by the present invention first integrates chips and passive devices and then packages the chips and the passive devices together, thereby forming a final packaged product having not single-chip functionality but integrated-system functionality. Compared to current system-level packaging, highly integrated wafer-level packaging reduces such interfering factors as system-internal electric resistance and inductance, and accommodates the growing demand for lighter, thinner, shorter, and smaller semiconductor packaging.

Find Patent Forward Citations

Quick Actions:

Shi, Lei. (2016). Packaging method (U.S. Patent No. 9324583). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9324583

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…