The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 19, 2016

Filed:

Dec. 21, 2012
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Liwen Jin, Chandler, AZ (US);

Dilan Seneviratne, Phoenix, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H05K 1/18 (2006.01); H05K 3/46 (2006.01); H01L 23/538 (2006.01); H01L 23/498 (2006.01); H01L 21/683 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H05K 1/185 (2013.01); H01L 21/6835 (2013.01); H01L 23/49822 (2013.01); H01L 23/49894 (2013.01); H01L 23/5389 (2013.01); H01L 24/19 (2013.01); H05K 3/4682 (2013.01); H01L 2221/68345 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/73267 (2013.01); H05K 2203/0152 (2013.01);
Abstract

An example includes a die package including a microelectronic die having a lower die surface, an upper die surface parallel to the lower die surface, and a die side, the microelectronic die including an active region and an inactive region. The example optionally includes a release layer having a lower release layer surface, an upper release layer surface parallel to the lower release layer surface, and at least one release layer side, the release layer coupled with the upper surface of the microelectronic die in thermal communication with the inactive region of the die and electrically insulated from the active region. The example optionally includes an encapsulation material encapsulating the die side and the release layer side and lower release layer surface, the encapsulation material including a lower surface substantially parallel to the die lower surface and an upper surface substantially parallel to the die upper surface.


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