The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 19, 2016

Filed:

Jan. 08, 2013
Applicant:

Tokyo Electron Limited, Tokyo, JP;

Inventors:

Kozo Kai, Fuchu, JP;

Takamasa Chikuma, Nirasaki, JP;

Keiji Osada, Nirasaki, JP;

Chunmui Li, Nirasaki, JP;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/67 (2006.01); H01L 21/677 (2006.01);
U.S. Cl.
CPC ...
H01L 21/67265 (2013.01); H01L 21/67772 (2013.01);
Abstract

In STEP, a mapping operation is carried out by a mapping device. In STEP, based on position information for the wafer (W) detected by the mapping operation, it is determined whether or not a wafer (W) position is in an abnormal state or not. When the wafer position is determined to be in the abnormal state (Yes), a closing/opening operation, in which a FOUP door () is temporarily closed and then opened, is carried out in STEP. In STEP, the number of times the FOUP door () is closed/opened (in other words, the number of times a port door () is closed/opened) is counted, and in STEP, it is determined whether or not this count value is less than a preset value. If the count value is less than the preset value (Yes), the processing in STEP-STEPis repeated once again.


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