The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 19, 2016

Filed:

Dec. 23, 2013
Applicant:

John V. Lovelace, Irmo, SC (US);

Inventor:

John V. Lovelace, Irmo, SC (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/40 (2006.01); G11C 11/406 (2006.01); G11C 29/02 (2006.01); G11C 29/42 (2006.01); G11C 29/50 (2006.01); G11C 29/04 (2006.01);
U.S. Cl.
CPC ...
G11C 11/40607 (2013.01); G11C 29/023 (2013.01); G11C 29/028 (2013.01); G11C 29/42 (2013.01); G11C 29/50012 (2013.01); G11C 11/40 (2013.01); G11C 2029/0409 (2013.01); G11C 2029/0411 (2013.01); G11C 2211/4061 (2013.01); G11C 2211/4062 (2013.01);
Abstract

Techniques and mechanisms to dynamically adjustment a timing of commands to access a dynamic random access memory (DRAM). In an embodiment, a memory controller monitors an error rate of the DRAM and, based on such monitoring, identifies that the error rate is within a predetermined range. In response to the error rate being within the predetermined range, one or more signals are generated to dynamically modify a command timing setting. In another embodiment, modification of the command timing setting is to transition a memory controller from sending memory refresh commands successively at one rate to sending memory refresh commands successively at a different rate.


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