The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 12, 2016
Filed:
Oct. 02, 2015
Applicant:
United Microelectronics Corporation, Hsinchu, TW;
Inventors:
Kun-Yuan Lo, Tainan, TW;
Chih-Wei Yang, Kaohsiung, TW;
Cheng-Guo Chen, Changhua County, TW;
Rai-Min Huang, Taipei, TW;
Jian-Cun Ke, Tainan, TW;
Assignee:
UNITED MICROELECTRONICS CORPORATION, Hsinchu, TW;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 29/423 (2006.01); H01L 21/28 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 21/265 (2006.01); H01L 21/324 (2006.01);
U.S. Cl.
CPC ...
H01L 29/42376 (2013.01); H01L 21/265 (2013.01); H01L 21/28088 (2013.01); H01L 21/324 (2013.01); H01L 29/4966 (2013.01); H01L 29/66545 (2013.01); H01L 29/7833 (2013.01);
Abstract
A method for fabricating a field-effect transistor is provided. The method includes: forming a gate dielectric layer and a barrier layer on a substrate in sequence; forming a first silicon layer on and in contact with the barrier layer; performing a thermal treatment to form a silicide layer between the barrier layer and the first silicon layer; and forming a second silicon layer on and in contact with the first silicon layer.