The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 12, 2016

Filed:

Mar. 06, 2014
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Takashi Ando, Tuckahoe, NY (US);

Johnathan E. Faltermeier, Delanson, NY (US);

Su Chen Fan, Cohoes, NY (US);

Sivananda K. Kanakasabapathy, Niskayuna, NY (US);

Injo Ok, Loudonville, NY (US);

Tenko Yamashita, Schenectady, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/28 (2006.01); H01L 29/51 (2006.01); H01L 29/49 (2006.01); H01L 29/40 (2006.01); H01L 21/8234 (2006.01);
U.S. Cl.
CPC ...
H01L 21/28088 (2013.01); H01L 21/823456 (2013.01); H01L 29/401 (2013.01); H01L 29/4966 (2013.01); H01L 29/517 (2013.01);
Abstract

A method of forming a semiconductor structure includes depositing a gate dielectric layer lining a recess of a gate structure formed on a substrate with a first portion of the gate dielectric layer covering sidewalls of the recess and a second portion of the gate dielectric layer covering a bottom of the recess. A protective layer is deposited above the gate dielectric layer and then recessed selectively to the gate dielectric layer so that a top surface of the protective layer is below of the recess. The first portion of the gate dielectric layer is recessed until a top of the first portion of the gate dielectric layer is approximately coplanar with the top surface of the protective layer. The protective layer is removed and a conductive barrier is deposited above the recessed first portion of the gate dielectric layer to cut a diffusion path to the gate dielectric layer.


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