The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 05, 2016

Filed:

Mar. 23, 2015
Applicant:

Silicon Storage Technology, Inc., San Jose, CA (US);

Inventors:

Mandana Tadayoni, Cupertino, CA (US);

Nhan Do, Saratoga, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 29/66 (2006.01); H01L 29/788 (2006.01); H01L 29/423 (2006.01); H01L 29/778 (2006.01); H01L 21/28 (2006.01); H01L 27/115 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66825 (2013.01); H01L 21/28273 (2013.01); H01L 27/11521 (2013.01); H01L 29/42324 (2013.01); H01L 29/42328 (2013.01); H01L 29/66484 (2013.01); H01L 29/7781 (2013.01); H01L 29/788 (2013.01); H01L 29/7849 (2013.01);
Abstract

A memory device, and method of make same, having a substrate of semiconductor material of a first conductivity type, first and second spaced-apart regions in the substrate of a second conductivity type, with a channel region in the substrate therebetween, a conductive floating gate over and insulated from the substrate, wherein the floating gate is disposed at least partially over the first region and a first portion of the channel region, a conductive second gate laterally adjacent to and insulated from the floating gate, wherein the second gate is disposed at least partially over and insulated from a second portion of the channel region, and a stressor region of embedded silicon carbide formed in the substrate underneath the second gate.


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