The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 05, 2016

Filed:

Feb. 07, 2014
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Youngkuk Kim, Seoul, KR;

Ho-Kyun An, Seoul, KR;

Jaehyun Yeo, Bucheon-si, KR;

Badro Im, Yongin-si, KR;

HanJin Lim, Seoul, KR;

Sungho Jang, Seoul, KR;

Insang Jeon, Seoul, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8242 (2006.01); H01L 27/108 (2006.01); H01L 21/8234 (2006.01);
U.S. Cl.
CPC ...
H01L 27/10894 (2013.01); H01L 21/823412 (2013.01); H01L 21/823462 (2013.01); H01L 27/10814 (2013.01); H01L 27/10861 (2013.01);
Abstract

Semiconductor devices having a silicon-germanium channel layer and methods of forming the semiconductor devices are provided. The methods may include forming a silicon-germanium channel layer on a substrate in a peripheral circuit region and sequentially forming a first insulating layer and a second insulating layer on the silicon-germanium channel layer. The methods may also include forming a conductive layer on the substrate, which includes a cell array region and the peripheral circuit region, and patterning the conductive layer to form a conductive line in the cell array region and a gate electrode in the peripheral circuit region. The first insulating layer may be formed at a first temperature and the second insulating layer may be formed at a second temperature higher than the first temperature.


Find Patent Forward Citations

Loading…