The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 05, 2016

Filed:

Nov. 11, 2014
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Osvaldo Jorge Lopez, Annandale, NJ (US);

Jonathan Almeria Noquil, Bethlehem, PA (US);

Thomas Eugene Grebs, Bethlehem, PA (US);

Simon John Molloy, Allentown, PA (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/06 (2006.01); H01L 25/18 (2006.01); H01L 25/00 (2006.01); H01L 23/053 (2006.01); H01L 21/52 (2006.01); H01L 23/00 (2006.01); H01L 21/82 (2006.01); H01L 21/48 (2006.01);
U.S. Cl.
CPC ...
H01L 23/06 (2013.01); H01L 21/4803 (2013.01); H01L 21/52 (2013.01); H01L 21/82 (2013.01); H01L 23/053 (2013.01); H01L 24/83 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H01L 2224/83851 (2013.01); H01L 2924/01013 (2013.01); H01L 2924/01014 (2013.01); H01L 2924/01022 (2013.01); H01L 2924/01028 (2013.01); H01L 2924/01079 (2013.01); H01L 2924/04642 (2013.01); H01L 2924/04941 (2013.01); H01L 2924/05042 (2013.01); H01L 2924/05442 (2013.01); H01L 2924/10155 (2013.01); H01L 2924/1305 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/1425 (2013.01); H01L 2924/1427 (2013.01); H01L 2924/15 (2013.01);
Abstract

An electronic system comprises a first chip () of single-crystalline semiconductor including a first electronic device embedded in a second chip () of single-crystalline semiconductor shaped as a container having a slab () bordered by ridges (), and including a second electronic device. The nested chips are assembled in a container of low-grade silicon shaped as a slabbordered by retaining wallsand including conductive traces and terminals. The first electronic device is connected to the second electronic device by attaching the first chip onto the slab of the second chip; and the first and second electronic devices are connected to the container by embedding the second chip in the container, wherein the nested first and second chips operate as an electronic system and the container operates as the package of the system. For first and second devices as field effect transistors, the system is a power block.


Find Patent Forward Citations

Loading…