The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 05, 2016

Filed:

May. 06, 2014
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Bratin Saha, Santa Clara, CA (US);

Ali-Reza Adl-Tabatabai, San Jose, CA (US);

Quinn A. Jacobson, Sunnyvale, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/45 (2006.01); G06F 13/00 (2006.01); G06F 9/30 (2006.01); G06F 9/38 (2006.01); G06F 9/46 (2006.01); G06F 12/08 (2006.01);
U.S. Cl.
CPC ...
G06F 9/30087 (2013.01); G06F 9/3004 (2013.01); G06F 9/30043 (2013.01); G06F 9/30076 (2013.01); G06F 9/3834 (2013.01); G06F 9/3851 (2013.01); G06F 9/3861 (2013.01); G06F 9/467 (2013.01); G06F 12/0837 (2013.01); G06F 2212/62 (2013.01);
Abstract

A method and apparatus for enabling a Software Transactional Memory (STM) with precompiled binaries is herein described. Upon encountering an access operation in a transaction, an annotation field associated with a memory location referenced by the access is checked. In response to the memory location representing a previous similar access within the transaction, the access is performed without access barriers. However, if the annotation field is in a default state representing no previous access during a pendancy of the transaction, then a mode of the processor is determined. If the processor mode is in implicit mode, an access handler/barrier is asynchronously executed. Conversely, in an explicit mode, a flag is set instead of asynchronously executing the handler. In addition, during compilation convert explicit and convert implicit instructions are inserted to intelligently convert modes for precompiled and newly compiled binaries. Furthermore, new versions of newly compiled functions may be inserted to provide strong atomicity between previously and newly compiled functions.


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