The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 29, 2016
Filed:
Apr. 24, 2015
Applicant:
Sumitomo Electric Device Innovations, Inc., Yokohama-shi, Kanagawa, JP;
Inventors:
Assignee:
SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC., Yokohama-shi, JP;
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/302 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 21/02 (2006.01); H01L 29/778 (2006.01); H01L 21/311 (2006.01); H01L 29/20 (2006.01); H01L 29/417 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0611 (2013.01); H01L 21/0217 (2013.01); H01L 21/02104 (2013.01); H01L 21/02107 (2013.01); H01L 21/31116 (2013.01); H01L 29/0649 (2013.01); H01L 29/66045 (2013.01); H01L 29/66462 (2013.01); H01L 29/66568 (2013.01); H01L 29/7786 (2013.01); H01L 29/0692 (2013.01); H01L 29/2003 (2013.01); H01L 29/41758 (2013.01);
Abstract
A method for manufacturing a semiconductor device includes: forming a first active region, a second active region, an inactive region located between the first active region and the second active region, and a third active region, which crosses the inactive region to electrically connect the first active region to the second active region, in a semiconductor layer; forming an insulating layer on the semiconductor layer; and forming an opening selectively in the insulating layer by dry etching.