The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 29, 2016
Filed:
Feb. 26, 2010
Applicants:
IL Kwon Shim, Singapore, SG;
Seng Guan Chow, Singapore, SG;
Heap Hoe Kuan, Singapore, SG;
Inventors:
Assignee:
STATS ChipPAC Ltd., Singapore, SG;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/02 (2006.01); H01L 23/498 (2006.01); H01L 23/31 (2006.01); H01L 25/10 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49816 (2013.01); H01L 23/3128 (2013.01); H01L 25/105 (2013.01); H01L 23/49822 (2013.01); H01L 23/49827 (2013.01); H01L 2224/14181 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/1703 (2013.01); H01L 2224/17181 (2013.01); H01L 2224/17519 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01); H01L 2225/1023 (2013.01); H01L 2225/1058 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/15331 (2013.01); H01L 2924/3511 (2013.01);
Abstract
A method of manufacture of an integrated circuit packaging system includes: providing a package substrate having a component side and a system side; depositing a solder resist layer on the component side of the package substrate; patterning groups of access openings and a die mount opening in the solder resist layer; attaching an integrated circuit die in the die mount opening; forming conductive contacts in the access openings; and attaching system interconnects to the system side of the package substrate including controlling a coplanarity of the system interconnects by the solder resist layer.