The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 22, 2016

Filed:

Feb. 12, 2014
Applicant:

Synopsys Inc., Mountain View, CA (US);

Inventors:

Brian S. Gordon, San Jose, CA (US);

Rafik Marutyan, Pleasanton, CA (US);

John Kim, Santa Clara, CA (US);

Christophe P. Suzor, Mimet, FR;

Assignee:

Synopsys Inc., Mountain View, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 15/04 (2006.01); G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5081 (2013.01); G06F 2217/06 (2013.01); G06F 2217/68 (2013.01);
Abstract

A method, system or computer usable program product for automatically identifying layout pattern candidates in selected regions for use in analyzing semiconductor device performance issues including identifying a set of target regions and a set of reference regions from a design layout; utilizing a processor to generate a reference baseline of layout patterns from the set of reference regions; utilizing the processor to compare a frequency profile of layout patterns in the set of target regions to a frequency profile of layout patterns in the reference baseline; and based on the comparison, utilizing the processor to identify candidate layout patterns from the set of target regions for further analysis.


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