The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 22, 2016

Filed:

Dec. 20, 2013
Applicants:

Alaa R. Alameldeen, Hillsboro, OR (US);

Niranjan L. Cooray, Folsom, CA (US);

Jayesh Gaur, Bangalore, IN (US);

Steven D. Pudar, Folsom, CA (US);

Manuel A. Aguilar Arreola, Folsom, CA (US);

Margareth E. Marrugo, El Dorado Hills, CA (US);

Chinnakrishnan Ballapuram, Milpitas, CA (US);

Inventors:

Alaa R. Alameldeen, Hillsboro, OR (US);

Niranjan L. Cooray, Folsom, CA (US);

Jayesh Gaur, Bangalore, IN (US);

Steven D. Pudar, Folsom, CA (US);

Manuel A. Aguilar Arreola, Folsom, CA (US);

Margareth E. Marrugo, El Dorado Hills, CA (US);

Chinnakrishnan Ballapuram, Milpitas, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/08 (2006.01); H03M 7/30 (2006.01); G06F 17/30 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0875 (2013.01); G06F 12/0802 (2013.01); G06F 17/30153 (2013.01); H03M 7/3086 (2013.01); H03M 7/3091 (2013.01); G06F 2212/401 (2013.01);
Abstract

A cache memory data compression and decompression technique is described. A processor device includes a memory controller unit (MCU) coupled to a main memory and a cache memory. The MCU includes a cache memory data compression and decompression module that compresses data received from the main memory. The compressed data may then be stored in the cache memory. The cache memory data compression and decompression module may also decompress data that is stored in the cache memory. For example, in response to a cache hit for data requested by a processor, the compressed data in the cache memory may be decompressed and subsequently read or operated upon by the processor.


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