The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 15, 2016
Filed:
May. 02, 2012
Se-yun Lim, Gyeonggi-do, KR;
Eun-seok Choi, Gyeonggi-do, KR;
Young-wook Lee, Gyeonggi-do, KR;
Won-joon Choi, Gyeonggi-do, KR;
Ki-hong Lee, Gyeonggi-do, KR;
Sang-bum Lee, Gyeonggi-do, KR;
Se-Yun Lim, Gyeonggi-do, KR;
Eun-Seok Choi, Gyeonggi-do, KR;
Young-Wook Lee, Gyeonggi-do, KR;
Won-Joon Choi, Gyeonggi-do, KR;
Ki-Hong Lee, Gyeonggi-do, KR;
Sang-Bum Lee, Gyeonggi-do, KR;
Hynix Semiconductor Inc., Gyeonggi-do, KR;
Abstract
A method for fabricating a non-volatile memory device includes alternately stacking a plurality of interlayer dielectric layers and a plurality of conductive layers over a substrate, etching the interlayer dielectric layers and the conductive layers to form a trench which exposes a surface of the substrate forming a first material layer over a resulting structure in which the trench is formed, forming a second material layer over the first material layer, removing portions of the second material layer and the first material layer formed on a bottom of the trench to expose the surface of the substrate, removing the second material layer, and burying a channel layer within the trench in which the second material layer is removed.