The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 15, 2016
Filed:
Apr. 09, 2012
Hirofumi Shinohara, Kanagawa, JP;
Yukio Nishida, Kanagawa, JP;
Katsuyuki Horita, Kanagawa, JP;
Tomohiro Yamashita, Kanagawa, JP;
Hidekazu Oda, Kanagawa, JP;
Hirofumi Shinohara, Kanagawa, JP;
Yukio Nishida, Kanagawa, JP;
Katsuyuki Horita, Kanagawa, JP;
Tomohiro Yamashita, Kanagawa, JP;
Hidekazu Oda, Kanagawa, JP;
Renesas Electronics Corporation, Tokyo, JP;
Abstract
MISFETs after the 32 nm technology node have a High-k gate insulating film and a metal gate electrode. Such MISFETs have the problem that the absolute value of the threshold voltage of n-MISFET and p-MISFET inevitably increases by the subsequent high temperature heat treatment. The threshold voltage is therefore controlled by forming various threshold voltage adjusting metal films on a High-k gate insulating film and introducing a film component from them into the High-k gate insulating film. The present inventors have however revealed that lanthanum or the like introduced into the High-k gate insulating film of the n-MISFET is likely to transfer to the STI region by the subsequent heat treatment. The semiconductor integrated circuit device according to the present invention is provided with an N channel threshold voltage adjusting element outward diffusion preventing region in the surface portion of the element isolation region below and at the periphery of the gate stack of the n-MISFET.