logo

For the Inventor, By the Inventor

The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9281243 B1

PDFFull Text
Date of Patent:
Mar. 08, 2016

Filed:

Feb. 04, 2014

Chip scale package structure and manufacturing method thereof

Applicant:

Xintec Inc., Zhongli, Taoyuan County, TW;

Inventors:

Chien-Hung Liu, New Taipei, TW;

Ying-Nan Wen, Hsinchu, TW;

Assignee:

XINTEC INC., Taoyuan, TW;

Attorney:

Liu & Liu

Primary Examiner:

Jarrett Stark

Assistant Examiner:

Shahed Ahmed

Int. Cl.
CPC ...
H01L 23/495 (2006.01); H01L 21/78 (2006.01); H01L 23/00 (2006.01); H01L 23/552 (2006.01); B81B 7/00 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 21/78 (2013.01); B81B 7/0064 (2013.01); H01L 21/561 (2013.01); H01L 23/552 (2013.01); H01L 24/11 (2013.01); H01L 23/3114 (2013.01); H01L 2924/12042 (2013.01); H01L 2924/1461 (2013.01);
Abstract

A chip scale package structure includes a chip, a dam unit, a board body, a plurality of first conductors, an encapsulating glue, a plurality of first conductive layers, an isolation layer, and a plurality of first electrodes. The dam unit is disposed on the surface of the chip. The board body is located on the dam unit. The first conductors are respectively in electrical contact with the conductive pads of the chip. The encapsulating glue covers the surface of the chip, and the board body and the first conductors are packaged in the encapsulating glue. The first conductive layers are located on the surface of the encapsulating glue opposite to the chip and respectively in electrical contact with the first conductors. The isolation layer is located on the encapsulating glue and the first conductive layers. The first electrodes are respectively in electrical contact with the first conductive layers.

Find Patent Forward Citations

Liu, Chien-Hung. (2016). Chip scale package structure and manufacturing method thereof (U.S. Patent No. 9281243). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9281243

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…