The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 01, 2016

Filed:

Feb. 07, 2013
Applicants:

Jay-bok Choi, Gyeonggi-do, KR;

Yoo-sang Hwang, Suwon-si, KR;

Ah-young Kim, Seoul, KR;

Ye-ro Lee, Seoul, KR;

Gyo-young Jin, Seoul, KR;

Hyeong-sun Hong, Gyeonggi-do, KR;

Inventors:

Jay-Bok Choi, Gyeonggi-do, KR;

Yoo-Sang Hwang, Suwon-si, KR;

Ah-Young Kim, Seoul, KR;

Ye-Ro Lee, Seoul, KR;

Gyo-Young Jin, Seoul, KR;

Hyeong-sun Hong, Gyeonggi-do, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Suwon-Si, Gyeonggi-Do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/44 (2006.01); H01L 21/336 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 27/108 (2006.01); H01L 27/02 (2006.01);
U.S. Cl.
CPC ...
H01L 29/42312 (2013.01); H01L 27/10814 (2013.01); H01L 27/10823 (2013.01); H01L 27/10855 (2013.01); H01L 27/10876 (2013.01); H01L 27/10885 (2013.01); H01L 27/10888 (2013.01); H01L 29/4236 (2013.01); H01L 29/66621 (2013.01); H01L 27/0207 (2013.01);
Abstract

A method of fabricating a semiconductor device comprises forming a first and a second parallel field regions in a substrate, the parallel field regions are extended in a first direction, forming a first and a second gate capping layer in a first and a second gate trench formed in the substrate respectively, removing the gate capping layers partially so that a first landing pad hole is expanded to overlap the gate capping layers buried in the substrate partially, forming a landing pad material layer in the first space, and forming a bit line contact landing pad by planarizing the landing pad material layer to the level of top surfaces of the capping layers.


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