The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 01, 2016
Filed:
Jan. 27, 2014
Applicant:
United Microelectronics Corp., Hsin-Chu, TW;
Inventors:
Duan Quan Liao, Singapore, SG;
Yikun Chen, Singapore, SG;
Ching Hwa Tey, Singapore, SG;
Xiao Zhong Zhu, Singapore, SG;
Assignee:
UNITED MICROELECTRONICS CORP., Science-Based Industrial Park, Hsin-Chu, TW;
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/94 (2006.01); H01L 49/02 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/532 (2006.01); H01L 27/108 (2006.01);
U.S. Cl.
CPC ...
H01L 28/75 (2013.01); H01L 21/76807 (2013.01); H01L 23/5223 (2013.01); H01L 23/5329 (2013.01); H01L 23/53238 (2013.01); H01L 23/53295 (2013.01); H01L 27/10852 (2013.01); H01L 28/91 (2013.01); H01L 27/10808 (2013.01);
Abstract
A capacitor structure includes a substrate with a plurality of dielectric layers sequentially formed thereon, a trench formed in the dielectric layers, wherein the trench is composed of at least two interconnected dual damascene recesses, each dual damascene recess formed in one dielectric layer; and a capacitor multilayer disposed on the sidewall of the trench.