The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 01, 2016

Filed:

Mar. 28, 2014
Applicants:

Harold Ryan Chase, Mesa, AZ (US);

Mathew J Manusharow, Phoenix, AZ (US);

Mihir K Roy, Chandler, AZ (US);

Inventors:

Harold Ryan Chase, Mesa, AZ (US);

Mathew J Manusharow, Phoenix, AZ (US);

Mihir K Roy, Chandler, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 25/065 (2006.01); H01L 23/13 (2006.01); H01L 23/538 (2006.01); H01L 23/00 (2006.01); H01L 21/56 (2006.01); H01L 21/768 (2006.01); H01L 23/31 (2006.01); H01L 25/00 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0652 (2013.01); H01L 21/56 (2013.01); H01L 21/768 (2013.01); H01L 23/13 (2013.01); H01L 23/3157 (2013.01); H01L 23/5386 (2013.01); H01L 23/5389 (2013.01); H01L 24/19 (2013.01); H01L 25/0657 (2013.01); H01L 25/50 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/2919 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/81005 (2013.01); H01L 2224/81203 (2013.01); H01L 2224/83005 (2013.01); H01L 2224/83855 (2013.01); H01L 2224/92125 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06548 (2013.01); H01L 2225/06555 (2013.01); H01L 2924/1433 (2013.01); H01L 2924/14335 (2013.01); H01L 2924/15153 (2013.01); H01L 2924/15192 (2013.01); H01L 2924/18162 (2013.01);
Abstract

Some embodiments relate to an electronic package. The electronic package includes a substrate that includes a plurality of buildup layers. A first die is embedded in one of the buildup layers on one side of the substrate. A second die is bonded to the substrate within a cavity on an opposing side of the substrate. The first die and the second die may be electrically connected to conductors within the plurality of buildup layers. Other embodiments relate to method of connecting a first die to a second die to form an electronic package. The method includes attaching a first die to a core and fabricating a substrate onto the core. The method further includes creating a cavity in another of the buildup layers on an opposing side of the substrate and attaching a second die to the substrate within the cavity.


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