The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 01, 2016

Filed:

Mar. 26, 2014
Applicants:

Wei-sheng Lei, San Jose, CA (US);

James S. Papanu, San Rafael, CA (US);

Aparna Iyer, Sunnyvale, CA (US);

Brad Eaton, Menlo Park, CA (US);

Ajay Kumar, Cupertino, CA (US);

Inventors:

Wei-Sheng Lei, San Jose, CA (US);

James S. Papanu, San Rafael, CA (US);

Aparna Iyer, Sunnyvale, CA (US);

Brad Eaton, Menlo Park, CA (US);

Ajay Kumar, Cupertino, CA (US);

Assignee:

Applied Materials, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/78 (2006.01); H01L 23/544 (2006.01);
U.S. Cl.
CPC ...
H01L 21/78 (2013.01); H01L 23/544 (2013.01);
Abstract

Approaches for front side laser scribe plus backside bump formation and laser scribe and plasma etch dicing process are described. For example, a method of dicing a semiconductor wafer having integrated circuits on a front side thereof involves forming first scribe lines on the front side, between the integrated circuits, with a first laser scribing process. The method also involves forming arrays of metal bumps on a backside of the semiconductor wafer, each array corresponding to one of the integrated circuits. The method also involves forming second scribe lines on the backside, between the arrays of metal bumps, with a second laser scribing process, wherein the second scribe lines are aligned with the first scribe lines. The method also involves plasma etching the semiconductor wafer through the second scribe lines to singulate the integrated circuits.


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