The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 01, 2016
Filed:
Aug. 22, 2013
Applicant:
Freescale Semiconductor, Inc., Austin, TX (US);
Inventors:
Asanga H Perera, West Lake Hills, TX (US);
Sung-Taeg Kang, Austin, TX (US);
Jane A Yater, Austin, TX (US);
Cheong Min Hong, Austin, TX (US);
Assignee:
FREESCALE SEMICONDUCTOR,INC., Austin, TX (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 21/28 (2006.01); H01L 29/423 (2006.01); H01L 27/115 (2006.01); H01L 29/66 (2006.01); H01L 29/788 (2006.01);
U.S. Cl.
CPC ...
H01L 21/28273 (2013.01); H01L 27/11534 (2013.01); H01L 29/42332 (2013.01); H01L 29/66825 (2013.01); H01L 29/7881 (2013.01);
Abstract
A process integration is disclosed for fabricating non-volatile memory (NVM) cells (--) on a first flash cell substrate area () which are encapsulated in one or more planar dielectric layers () prior to forming an elevated substrate () on a second CMOS transistor area () on which high-k metal gate electrodes (--) are formed using a gate-last HKMG CMOS process flow without interfering with the operation or reliability of the NVM cells.