The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 01, 2016

Filed:

Jul. 30, 2010
Applicants:

Yi-tzu Chen, Hsin-Chu, TW;

Bin-hau Lo, Hsin-Chu, TW;

Tsai-hsin Lai, Jhubei, TW;

Pey-huey Chen, Baoshan Township, TW;

Hau-tai Shieh, Hsin-Chu, TW;

Inventors:

Yi-Tzu Chen, Hsin-Chu, TW;

Bin-Hau Lo, Hsin-Chu, TW;

Tsai-Hsin Lai, Jhubei, TW;

Pey-Huey Chen, Baoshan Township, TW;

Hau-Tai Shieh, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/40 (2006.01); G11C 11/4097 (2006.01); G11C 5/06 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4097 (2013.01); G11C 5/063 (2013.01);
Abstract

Apparatus and methods for providing a high density memory array with reduced read access time are disclosed. Multiple split bit lines are arranged along columns of adjacent memory bit cells. A multiple input sense amplifier is coupled to the multiple split bit lines. The loading on the multiple split bit line is reduced, and the corresponding read speed of the memory array is enhanced over the prior art. The sense amplifier and the memory bit cells have a common cell pitch layout height so that no silicon area penalty arises due to the use of the multiple split bit lines and sense amplifiers. Increased memory array efficiency is achieved.


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