The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 23, 2016
Filed:
Jul. 29, 2013
Applicant:
Fujitsu Limited, Kawasaki-shi, Kanagawa, JP;
Inventors:
Assignee:
FUJITSU LIMITED, Kawasaki, JP;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/00 (2006.01); H01L 29/778 (2006.01); H01L 29/20 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/10 (2006.01); H01L 29/15 (2006.01); B82Y 10/00 (2011.01);
U.S. Cl.
CPC ...
H01L 29/778 (2013.01); B82Y 10/00 (2013.01); H01L 29/1075 (2013.01); H01L 29/15 (2013.01); H01L 29/2003 (2013.01); H01L 29/42372 (2013.01); H01L 29/66462 (2013.01); H01L 29/7787 (2013.01);
Abstract
A semiconductor apparatus includes: a substrate; a buffer layer formed on the substrate; a strained layer superlattice buffer layer formed on the buffer layer; an electron transit layer formed of a semiconductor material on the strained layer superlattice buffer layer; and an electron supply layer formed of a semiconductor material on the electron transit layer; the strained layer superlattice buffer layer being an alternate stack of first lattice layers including AlN and second lattice layers including GaN; the strained layer superlattice buffer layer being doped with one, or two or more impurities selected from Fe, Mg and C.