The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 23, 2016
Filed:
Dec. 23, 2011
Jayashankar Bharadwaj, Saratoga, CA (US);
Victor W. Lee, Santa Clara, CA (US);
Kim Daehyun, San Jose, CA (US);
Nalini Vasudevan, Sunnyvale, CA (US);
Tin-fook Ngai, San Jose, CA (US);
Albert Hartono, Santa Clara, CA (US);
Sara S. Baghsorkhi, San Jose, CA (US);
Jayashankar Bharadwaj, Saratoga, CA (US);
Victor W. Lee, Santa Clara, CA (US);
Kim Daehyun, San Jose, CA (US);
Nalini Vasudevan, Sunnyvale, CA (US);
Tin-Fook Ngai, San Jose, CA (US);
Albert Hartono, Santa Clara, CA (US);
Sara S. Baghsorkhi, San Jose, CA (US);
INTEL CORPORATION, Santa Clara, CA (US);
Abstract
An apparatus and method are described for detecting and responding to fault conditions in a processor. For example, one embodiment of a method comprises: reading each active element in succession from a first vector register, each active element specifying an address for a gather or load operation; detecting one or more fault conditions associated with one or more of the active elements; for each active element read in succession prior to a detected fault condition on an element other than the first active element, storing the data loaded from an address associated with the active element in a first output vector register; and for each active element associated with the detected fault condition and following the detected fault condition, setting a bit in an output mask register to indicate the detected fault condition.