The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 16, 2016

Filed:

May. 01, 2015
Applicant:

Ibiden Co., Ltd., Ogaki-shi, JP;

Inventors:

Yasushi Inagaki, Ogaki, JP;

Yasuhiro Takahashi, Ogaki, JP;

Satoshi Kurokawa, Ogaki, JP;

Assignee:

IBIDEN CO., LTD., Ogaki-shi, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/00 (2006.01); H01P 3/08 (2006.01); H05K 1/11 (2006.01); H05K 1/18 (2006.01); H05K 1/02 (2006.01);
U.S. Cl.
CPC ...
H01P 3/081 (2013.01); H05K 1/0213 (2013.01); H05K 1/111 (2013.01); H05K 1/181 (2013.01); H05K 2201/10159 (2013.01);
Abstract

A package substrate includes a core substrate, a first buildup layer and a second buildup layer. The first buildup layer includes an uppermost interlayer, an upper inner interlayer, an uppermost conductive layer including first pads and second pads, an upper first conductive layer, an upper second conductive layer, vias formed through the uppermost interlayer and connecting the upper first conductive layer and the second pads, and skip vias formed through the uppermost and upper inner interlayers and connecting the uppermost and upper second conductive layers. The second buildup layer includes a lowermost interlayer, a lower inner interlayer, a lowermost conductive layer including third pads, a lower first conductive layer, a lower second conductive layer, vias formed through the lowermost interlayer and connecting the lower first conductive layer and third pads, and skip vias formed through the lowermost and lower inner interlayers and connecting the lowermost and lower second conductive layers.


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