The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 16, 2016

Filed:

Nov. 18, 2009
Applicants:

Renee T. MO, Briarcliff Manor, NY (US);

Wesley C. Natzle, New Paltz, NY (US);

Vijay Narayanan, New York, NY (US);

Jeffrey W. Sleight, Ridgefield, CT (US);

Inventors:

Renee T. Mo, Briarcliff Manor, NY (US);

Wesley C. Natzle, New Paltz, NY (US);

Vijay Narayanan, New York, NY (US);

Jeffrey W. Sleight, Ridgefield, CT (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 21/28 (2006.01); H01L 29/49 (2006.01); H01L 29/51 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 21/28088 (2013.01); H01L 29/4966 (2013.01); H01L 29/517 (2013.01); H01L 29/6659 (2013.01); H01L 29/7833 (2013.01);
Abstract

A transistor is provided that includes a silicon layer with a source region and a drain region, a gate stack disposed on the silicon layer between the source region and the drain region, an L shaped gate encapsulation layer disposed on sidewalls of the gate stack, and a spacer disposed above the horizontal portion of the gate encapsulation layer and adjacent to the vertical portion of the gate encapsulation layer. The gate stack has a first layer of high dielectric constant material, a second layer comprising a metal or metal alloy, and a third layer comprising silicon or polysilicon. The gate encapsulation layer has a vertical portion covering the sidewalls of the first, second, and third layers of the gate stack and a horizontal portion covering a portion of the silicon layer that is adjacent to the gate stack.


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