The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 16, 2016

Filed:

Oct. 31, 2013
Applicant:

Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;

Inventors:

Chiting Cheng, Taichung, TW;

Chien-Kuo Su, Kaohsiung County, TW;

Cheng Hung Lee, Hsinchu, TW;

Jonathan Tsung-Yung Chang, Hsinchu, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 11/419 (2006.01); G11C 11/413 (2006.01); H01L 27/11 (2006.01); G11C 5/14 (2006.01); G11C 16/30 (2006.01); G11C 7/02 (2006.01); G11C 8/08 (2006.01); G11C 11/418 (2006.01);
U.S. Cl.
CPC ...
G11C 11/419 (2013.01); G11C 5/14 (2013.01); G11C 7/02 (2013.01); G11C 8/08 (2013.01); G11C 11/413 (2013.01); G11C 11/418 (2013.01); G11C 16/30 (2013.01); H01L 27/11 (2013.01);
Abstract

A semiconductor memory device comprises an array of memory cells arranged in rows and columns, control lines coupled to the rows of memory cells for accessing the memory cells, conductive lines coupled to the rows of memory cells for powering the memory cells, and a control circuit configured to maintain non-selected conductive lines at a first voltage level and boost a selected conductive line to a second voltage level in an access operation, the second voltage level being higher than the first voltage level.


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