The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 09, 2016

Filed:

Dec. 10, 2008
Applicants:

Rui Huang, Singapore, SG;

Heap Hoe Kuan, Singapore, SG;

Yaojian Lin, Singapore, SG;

Seng Guan Chow, Singapore, SG;

Inventors:

Rui Huang, Singapore, SG;

Heap Hoe Kuan, Singapore, SG;

Yaojian Lin, Singapore, SG;

Seng Guan Chow, Singapore, SG;

Assignee:

STATS ChipPAC, Ltd., Singapore, SG;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 49/02 (2006.01); H01L 23/31 (2006.01); H01L 21/56 (2006.01); H01L 23/495 (2006.01); H01L 23/498 (2006.01); H01L 23/552 (2006.01); H01L 23/66 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2006.01); H01L 25/10 (2006.01); H01L 25/00 (2006.01); H01L 25/03 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3128 (2013.01); H01L 21/561 (2013.01); H01L 21/568 (2013.01); H01L 23/495 (2013.01); H01L 23/49506 (2013.01); H01L 23/49541 (2013.01); H01L 23/49816 (2013.01); H01L 23/552 (2013.01); H01L 23/66 (2013.01); H01L 24/27 (2013.01); H01L 24/29 (2013.01); H01L 24/32 (2013.01); H01L 24/49 (2013.01); H01L 24/83 (2013.01); H01L 24/97 (2013.01); H01L 25/03 (2013.01); H01L 25/0657 (2013.01); H01L 25/105 (2013.01); H01L 25/50 (2013.01); H01L 24/48 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/16235 (2013.01); H01L 2224/27416 (2013.01); H01L 2224/27436 (2013.01); H01L 2224/2919 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/48247 (2013.01); H01L 2224/48465 (2013.01); H01L 2224/4903 (2013.01); H01L 2224/49051 (2013.01); H01L 2224/73265 (2013.01); H01L 2224/83136 (2013.01); H01L 2224/83191 (2013.01); H01L 2224/83192 (2013.01); H01L 2224/83385 (2013.01); H01L 2224/83856 (2013.01); H01L 2224/92 (2013.01); H01L 2224/97 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/1023 (2013.01); H01L 2225/1058 (2013.01); H01L 2225/1088 (2013.01); H01L 2924/00011 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/0103 (2013.01); H01L 2924/01004 (2013.01); H01L 2924/014 (2013.01); H01L 2924/01005 (2013.01); H01L 2924/0105 (2013.01); H01L 2924/01006 (2013.01); H01L 2924/01013 (2013.01); H01L 2924/01014 (2013.01); H01L 2924/01023 (2013.01); H01L 2924/01028 (2013.01); H01L 2924/01029 (2013.01); H01L 2924/01047 (2013.01); H01L 2924/01073 (2013.01); H01L 2924/01074 (2013.01); H01L 2924/01078 (2013.01); H01L 2924/01079 (2013.01); H01L 2924/01082 (2013.01); H01L 2924/01083 (2013.01); H01L 2924/01322 (2013.01); H01L 2924/04941 (2013.01); H01L 2924/04953 (2013.01); H01L 2924/0665 (2013.01); H01L 2924/09701 (2013.01); H01L 2924/12041 (2013.01); H01L 2924/12044 (2013.01); H01L 2924/1306 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/14 (2013.01); H01L 2924/1433 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/181 (2013.01); H01L 2924/1815 (2013.01); H01L 2924/19015 (2013.01); H01L 2924/19041 (2013.01); H01L 2924/19042 (2013.01); H01L 2924/19043 (2013.01); H01L 2924/19103 (2013.01); H01L 2924/19104 (2013.01); H01L 2924/19107 (2013.01); H01L 2924/3025 (2013.01); H01L 2924/30105 (2013.01);
Abstract

A semiconductor device has a conductive layer formed on a substrate. The conductive layer has a first portion constituting contact pads and a second portion constituting an integrated passive device such as an inductor. A spacer is formed on the substrate around the second portion of the conductive layer. The spacer can be insulating material or conductive material for shielding. A semiconductor die is mounted to the spacer. An electrical connection is formed between contact pads on the semiconductor die and the contact pads on the substrate. An encapsulant is formed around the semiconductor die, electrical connections, spacer, and conductive layer. The substrate is removed to expose the conductive layer. An interconnect structure is formed on the backside of the substrate. The interconnect structure is electrically connected to the conductive layer. The semiconductor device can be integrated into a package.


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