The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 02, 2016

Filed:

Jul. 11, 2014
Applicant:

Shinko Electric Industries Co., Ltd., Nagano-shi, Nagano, JP;

Inventors:

Kentaro Kaneko, Nagano, JP;

Katsuya Fukase, Nagano, JP;

Kazuhiro Kobayashi, Nagano, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/03 (2006.01); H05K 1/00 (2006.01); H05K 1/09 (2006.01); H05K 7/10 (2006.01); H05K 3/40 (2006.01); H05K 3/46 (2006.01);
U.S. Cl.
CPC ...
H05K 3/4007 (2013.01); H05K 3/465 (2013.01); H05K 2203/0392 (2013.01); H05K 2203/1461 (2013.01); H05K 2203/1563 (2013.01);
Abstract

A wiring substrate includes an insulating layer, a first pad, and a solder resist layer. The first pad is embedded in the insulating layer. The solder resist layer is provided on an upper surface of the insulating layer. The solder resist layer is formed with an opening portion through which the recess portion is exposed. An adjacent portion of the solder resist layer adjacent to a peripheral portion of the opening portion covers a peripheral portion of the upper surface of the first pad and protrudes from the peripheral portion of the upper surface of the first pad toward the center portion of the first pad so as to cover above the recess portion. Surfaces of the first pad being in contact with the insulating layer are smaller in roughness than the upper surface of the insulating layer and the peripheral portion of the upper surface of the first pad.


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