Integrated clock architecture for improved testing

Abstract

A computer system includes a first on-chip controller and a second on-chip controller, both connected to a control element. In normal operation, the first and second on-chip controllers operate in different clock domains. During testing, the control element causes each on-chip controller to generate a substantially similar clock signal. The substantially similar clock signals are used to test substantially similar test circuitry connected to each on-chip controller, thereby reducing overhead associated with testing. A delay may be incorporated into the path of the clock signal of one of the on-chip controllers to reduce instantaneous power draw during testing.